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alexforencich / verilog-ethernet

Verilog Ethernet components for FPGA implementation
MIT License
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UDP flow #191

Open anushkaASB opened 9 months ago

anushkaASB commented 9 months ago

@alexforencich "First and foremost, I'd like to extend my sincere gratitude for providing this invaluable resource, which serves as a cornerstone for countless projects. Thank you.

In regards to testing the UDP functionality on the FPGA, I've meticulously analyzed the UDP source code within Vivado. Thus far, I've completed synthesis, implementation, bitstream generation, and FPGA programming. Despite these efforts, I'm encountering difficulties in retrieving data on the FPGA.

Could you please advise on the correct flow for verifying the functionality of the udp_test.py script? Any guidance or insights would be greatly appreciated.

Thank you in advance for your assistance."

lizajoseph commented 9 months ago

Hi Anushka,

I have also generated the bitstream for this design. But I am not sure how to program the bitfile on FPGA and how to test the logic on FPGA? Could you please let me know if you have the steps to validate the design on the FPGA board