alexforencich / verilog-ethernet

Verilog Ethernet components for FPGA implementation
MIT License
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Is there a block diagram available for the UDP echo server design ? #201

Open lizajoseph opened 7 months ago

lizajoseph commented 7 months ago

Is there any block diagram available for this design? Currently only module descriptions are available and it would be helpful to understand the design with a block diagram to understand how the sub modules interact with each other.