alexforencich / verilog-ethernet

Verilog Ethernet components for FPGA implementation
MIT License
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ADM-PCIE-9V3 example not working #224

Closed harris-chris closed 1 month ago

harris-chris commented 1 month ago

Hello

(edited because the first post had a simple mistake)

I'm trying to build the ADM-PCIE-9V3 example, and having some issues. I've done the following:

Could I check that this all sounds correct, and there's nothing obviously wrong with my process above?

elliotpotts commented 1 month ago

I have also been unable to get the ADM-PCIE-9V3 example working.

harris-chris commented 1 month ago

Closing this because my problem was entirely unrelated to this repo. If anyone else has a problem with the ADM-PCIE-9V3 card, check the card's settings with the avr2util supplied by Alpha Data, it's possible to permanently alter the QSFP28 interface clock (which is what somebody had done to my card, and could then be re-set by the same utility).

alexforencich commented 1 month ago

Nice work sorting that out, never knew you could do that myself. Although I suppose if you can change it back, it's not permanent, only nonvolatile. Honestly with the fractional-N support in the QPLLs, there should be no reason to change the clock frequency, unless maybe you're doing something really strange.

elliotpotts commented 1 month ago

To add, the utility can be downloaded and built from here: https://support.alpha-data.com/pub/firmware/utilities/linux/ https://support.alpha-data.com/pub/firmware/utilities/windows/