Closed harris-chris closed 1 month ago
I have also been unable to get the ADM-PCIE-9V3 example working.
Closing this because my problem was entirely unrelated to this repo. If anyone else has a problem with the ADM-PCIE-9V3 card, check the card's settings with the avr2util
supplied by Alpha Data, it's possible to permanently alter the QSFP28 interface clock (which is what somebody had done to my card, and could then be re-set by the same utility).
Nice work sorting that out, never knew you could do that myself. Although I suppose if you can change it back, it's not permanent, only nonvolatile. Honestly with the fractional-N support in the QPLLs, there should be no reason to change the clock frequency, unless maybe you're doing something really strange.
To add, the utility can be downloaded and built from here: https://support.alpha-data.com/pub/firmware/utilities/linux/ https://support.alpha-data.com/pub/firmware/utilities/windows/
Hello
(edited because the first post had a simple mistake)
I'm trying to build the ADM-PCIE-9V3 example, and having some issues. I've done the following:
cd
-ed toexample/ADM_PCIE_9V3/fpga_25g
SUBDIRS = fpga_10g
in./Makefile
, because I'd like to build the 10Gb/s version; beyond this there are no other changes to the repomake
. No errors are reported and there doesn't seem to be anything unusual on the output. It looks like it all works fine.cd
-ed to./fpga_10g
, then runmake program
to program the FPGA (this step seems to be required, but is not mentioned in the documentation).ethtool
, no link can be detected, the speed isUnknown!
.qsfp_0_rx_block_lock
. It does not light up. So presumably the PHY layer can't establish a lock.Could I check that this all sounds correct, and there's nothing obviously wrong with my process above?