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alexforencich / verilog-ethernet

Verilog Ethernet components for FPGA implementation
MIT License
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Deembedded Blockdesign Arty A7 Echo-Server #233

Open Felolie opened 2 weeks ago

Felolie commented 2 weeks ago

Hey there, I'm new to working with FPGAs. I want to transfer Data from the IO's to the PC via Ethernet for that purpose I needed an Ethernet-Core and a college just recommended me that one here. So for my first steps, I build the Example on my Linux (openSUSE Tumbleweed with Vivado-Suite 2024.1). That worked well, because I want to use the Blocks (It's mandatory), I used the Verilog-Files for creation of Modules. For that to work, I made some miner changes, because else I couldn't create the Blocks. The Changes: udp_complete: ARP_REQUEST_TIMEOUT was a too big number, so I wrote the keyword time in advance of the Parameter. eth_axis_rx/tx: The Program said not all Variables have an initial value, for that I copied them to the global path of the file

Then I created the schematic as shown, for that I used a more integrated version of the Echo-Server and looked up the Elaborated Design. That's the Level of deembedding I need. I can run everything till generating bit stream. But the Server don't respond. Bildschirmfoto vom 2024-10-28 09-14-26

Here the Verilogfiles I implemented. Bildschirmfoto vom 2024-10-28 09-16-18

The Message box shown below. The critical Warnings in the top wasn't until now a problem, it worked fin in an earlier attempt. Bildschirmfoto vom 2024-10-28 12-13-16

I hope my Problem is clear, and I didn't waste your time. I looked for a similar Problem but didn't find a solution. Furthermore, I am at your disposal for further questions

Best Wishes Clas

Felolie commented 3 days ago

The set_property error could I eliminate with commenting that line out, and then I can generate a bitstream.