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alexforencich / verilog-ethernet

Verilog Ethernet components for FPGA implementation
MIT License
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porting to VU440 with 88E1116 #81

Open Albert-Siu opened 3 years ago

Albert-Siu commented 3 years ago

I try to port to VU440 but fail to make the project. My steps is as below. Please provide some advice. Thx.

  1. Copy from project VCU108/fpga_1g to VU440/fpga_1g/
  2. Type make to build the original VCU108 project
  3. Modify device part number and pin assignment
  4. Build the project again

I fail in step 2 which is make the project with the original VCU108/fpga_1g/. The error message is as below:

make all cd fpga && make make[1]: Entering directory /home/XXXX/project/fpga/eth/mod/verilog-ethernet-master/example/VU440/fpga_1g/fpga' make[1]: *** No rule to make targetfpga.bit', needed by fpga'. Stop. make[1]: Leaving directory/home/XXXX/project/fpga/eth/mod/verilog-ethernet-master/example/VU440/fpga_1g/fpga' make: *** [fpga] Error 2

alexforencich commented 3 years ago

Sounds like a missing file or broken symlink. Does the VCU108 design build? Does your copy build, before making any modifications?

Albert-Siu commented 3 years ago

Yes. There are some symlink broken. I change to use KC705 example as a reference. As my PHY only support RGMII.

The next step is change device part number and pin assignment. Thx.