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algorhtym / riscv-resources

An organized and comprehensive library of resources for the RISC-V community and anyone interested in getting involved with the RISC-V ecosystem, relevantly categorized based on topics and knowledge/experience level, built by the RISC-V community.
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[New RISC-V Tutorial Resource] - learn-FPGA episode II: pipelining #4

Open BrunoLevy opened 11 months ago

BrunoLevy commented 11 months ago

Resource Title

learn-FPGA episode II: pipelining

Resource Description

This tutorial explains how to transform the basic softcore from episode I into an efficient pipelined processor. The tutorial follows a step-by-step approach, starting from a 5-states processor, transforming the states into stages, and solving data and control hazards by first observing what happens in real programs thanks to the included debugger/disassembler. Then it is explained how to gain more performance using register forwarding. Finally, branch prediction is introduced, from the simplest static branch prediction to more elaborate ones (gshare). The effect of the different optimizations are demonstrated using different codes (the classical dhrystones and coremark benchmarks, and a program that computes an image using raytracing).

Resource Link

https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/TUTORIALS/FROM_BLINKER_TO_RISCV/PIPELINE.md

Required Prerequisites (Optional)

It is highly recommended to read episode I before episode II !

Additional Details (Optional)

The resulting core (TordBoyau) with some additional optimizations is here

algorhtym commented 11 months ago

Thank you for your contribution. The issue submission link has been moved to RISC-V organization's GitHub repository. This resource is now added to that repository. Episode I was added to the beginner level learning path and episode II was placed in the intermediate learning path. Please let us know if you think any modification to this makes more sense.