algosup / 2024-2025-project-1-fpga-team-1

The goal of the FPGA project is to recreate a Frogger in Verilog.
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Technical_specification Issues nº1 #5

Closed Mamoru-fr closed 1 month ago

Mamoru-fr commented 1 month ago

What's written:

line 72 - [FPGA Board name] line 127 - D. Constraints line 132 - E. Risks and Assumptions line 139 - A. Graphic Convention** line 146 - reg [15:0] frog_sprite [0:255]; // Store 16x16 sprite data

What needs to be written:

line 72 - FPGA Go-board line 127 - D. Constraints line 132 - E. Risks and Assumptions line 139 - A. Graphic Convention line 146 - reg [31:0] frog_sprite [0:255]; // Store 32x32 sprite data

mathislebel commented 1 month ago

it is done