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algosup / 2024-2025-project-1-fpga-team-1

The goal of the FPGA project is to recreate a Frogger in Verilog.
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Functionnal Specification Issues N°1 #8

Closed Mamoru-fr closed 1 month ago

Mamoru-fr commented 1 month ago

You need to replace "design" by "sprite" on line 100 and 102.