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alhassanalbadri / systemverilog-linter

Robust SystemVerilog Linter and Formatter to enhance code quality and ensure standards compliance. Perfect for hardware designers seeking efficient verification and readable code.
http://verilog.alhassan.dev/
Apache License 2.0
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Format Module Instantiations #3

Open alhassanalbadri opened 5 months ago

alhassanalbadri commented 5 months ago

The linter currently formats such module definitions with no issue:

module x(
input logic test1,
output logic test2,
);
logic f;
assign f = x;

endmodule

But it does not support module instantiations such as:

adder Add1and2(
.op1(test),
.op2(test),
.result(output)
)

We can probably detect these by the format they're created in: ModuleName instName( ...params )

alhassanalbadri commented 5 months ago

With this commit: 71ed26d modules inst. are now detected but are not formatted as of yet.