Robust SystemVerilog Linter and Formatter to enhance code quality and ensure standards compliance. Perfect for hardware designers seeking efficient verification and readable code.
Incorporating a basic error detection mechanism. This feature will initially focus on identifying common syntax errors within user-provided SystemVerilog code. By doing so, it will provide users with immediate, actionable feedback to improve code accuracy and readability.
Todo List:
[x] Unclosed Blocks: Detect blocks that are opened, but never closed, such as using a begin block but not having a corresponding closing end statement.
[x] Unopened Blocks: Detect blocks that are ended before they are opened, having a endcase instruction but not having a corresponding case statement.
[x] Undeclared Variables: Catch instances where variables are used without prior declaration, this may cause unexpected implicit definitions with wrong bit sizes.
Expected Outcome:
By implementing these features, I expect a more seamless interface provided for the user. Highlighting lines with issues and pointing it out for users to fix.
alhassanalbadri
commented
2 months ago
Description:
Incorporating a basic error detection mechanism. This feature will initially focus on identifying common syntax errors within user-provided SystemVerilog code. By doing so, it will provide users with immediate, actionable feedback to improve code accuracy and readability.
Todo List:
beginblock but not having a corresponding closingendstatement.endcaseinstruction but not having a correspondingcasestatement.Expected Outcome:
By implementing these features, I expect a more seamless interface provided for the user. Highlighting lines with issues and pointing it out for users to fix.