Front panel layout

[micbeldyga]

First draft of front panel connectors placement.

From left to right:

1. USB C power input
2. SFP cage
3. stacked LEMO 00 - AC coupled LVDS clock
4. 2x SMA - AC coupled 800mVpp (LPECL) clock
5. 2x SMA - AC coupled 800mVpp (LPECL) x3/x4 clock
6. LED indicator for x3/x4 clock output selection
7. toggle switch for x3/x4 clock output selection

SMA staggered with 10.5mm spacing like in DIO_SMA project

It's a tight squeeze, especially around switch and LED indicator. Since SMAs shouldn't be placed any tighter, additional room must be found by moving LEMO, SFP and USB-C connectors

[gkasprow]

• [x] use only _P output from clock ICs - we need to have the same phase on all outputs
• [x] use LEMO00 but in diff version (EPG.00.302.NLN), connect to Bank 2 of IC1; unfortunately, they don't exist in the stacked version. Use one LEMO only - we need it for TCM only
• [x] add LC filter (1uH+22u||10u tantalum + FB 120R@100MHz + 22u) at the input of LDO to suppress RF components
• [x] The switch can be replaced by a DIP switch and available only from inside; make x2 x3 x4 options available.
• [x] route CLK1 output from IC3 to SMA (via 33Ohm series resistor). The second SMA stays connected to CLK2_P
• [x] connect P3V3 to individual ICs via FB
• [x] SFP may not like such a high signal; add 2x33 ohm in series with C8, C9
• [x] copy SMA positions and connector types from the DIO-SMA design.
• [x] MC100EPT21DTG doubles the jitter; consider using 1:1 transformer that will boost 2x800Vpp to 3.2Vpp, AC-copule it with IC3 and add bias resistors
• [x] you can use SMD LEDs - they are cheaper and can be placed anywhere; copy placement and diodes from Kasli
• [x] place the internal Molex connector at the board edge

[micbeldyga]

So to summarize, there should be the following connectors:

1. LEMO 00: SE, AC coupled Q0_P with reduced swing to LVDS level
2. SMA: SE, AC coupled Q1_P
3. LEMO 00: (EPG.00.302.NLN) DIFF, AC coupled. Routed from Bank2 (Q4-Q6) of IC1. Question: should it have limited output swing as well?
4. SFP connector
5. SMA: SE, DC coupled CLK1 output from IC3 (clock multiplier), LVTTL
6. SMA: SE, AC coupled CLK2 output from IC3, full LVPECL swing

[gkasprow]

1. No SE LEMO; only diff one with 40MHz LVDS clock
2. 2x SMA
3. LVDS levels
4. ACK
5. ACK
6. ACK

[micbeldyga]

The switch can be replaced by a DIP switch and available only from inside; make x2 x3 x4 options available.

Adding x2 option complicates things. Since each Sel0, Sel1 and Sel2 inputs is 'tri-level', i.e. it can discriminate between 0, Vcc/2 and Vcc, I'd place a ON-OFF-ON slide switch on each SelX pin and add a key/graphic on the silk screen with x2/x3/x4 settings marked

[gkasprow]

Great. I assume that adding LEDs on the panel gets complicated? Maybe some LMV339 would do the job..

[micbeldyga]

Right, now driving LEDs becomes really a crux of the project. Avoiding erroneous LED states may get tricky. Have to look into it

[gkasprow]

Let's do the opposite. Just make a 3-way switch, 3 LEDs, and a set of MOSFETs to control pull-up, pull-down, and Hi-Z states.

[gkasprow]

If you feel that it's overengineering, leave the x3/x4 option using the internal DPDT switch. We already have x2 output

[gkasprow]

by saying "we already have x2 output" I meant that we can use first bank of divider and set division to 1. That would require adding a dip swich.

[gkasprow]

We can also use this SP3T switch SS14MDP2

[micbeldyga]

by saying "we already have x2 output" I meant that we can use first bank of divider and set division to 1. That would require adding a dip swich.

Should x1/x2 option be available on any particular connector or should we have it as an option for the entire "Bank1", i.e. LEMO, 2x SMA and SFP?

Since there are outputs available in Bank2 and Bank3, we can rearrange the connections and have x1/x2 option available only for a specific connector.

[gkasprow]

Lemo and SFP will always be 40MHz; connect it to bank 1 SMAs scan be 40, 80 MHz, connect them to bank 2 Two other SMAs can be 80, 120, 160 MHz; we will drive Kaslis with them. Connect the multiplier to bank 3 That will cover all use cases However, if we can make it more versatile without complicating things much, let's do it. For unused LVPECL outputs it's fine to install just pulldown, no need to dissipate power with proper Thevenin termination

[micbeldyga]

left to right: USB-C power input 40MHz clock via SFP 40MHZ clock via LEMO connector 120/160MHz via 2x SMA, frequency selected with internal switch. Selection indicated with front panel LED 40/80MHz via 2x SMA, frequency selected with internal switch. Selection indicated with front panel LED