Closed dinkelk closed 1 year ago
The riscv64 toolchain supports 32 bit targets as well. Some notes about this and other things I discovered with the ESP32C3: https://www.reddit.com/r/ada/comments/xsglin/october_2022_what_are_you_working_on/iqopzas
@Fabien-Chouteau commented there about bare_runtime, which sounds like the right approach.
Ah! Very interesting. Thank you.
I was also working on a "patch" to bb-runtimes to add support for a not-yet-supported riscv architecture. Do you know how the bare_runtime crate compares, and why that might be a better approach?
With bare_runtime you set the architecture-specific gcc switches in alire.toml, rather than the RTS' runtime.xml. The bare_runtime README has some examples. I used bare_runtime for MSP430, you can see that here: https://github.com/JeremyGrosser/msp430test/blob/master/alire.toml#L22
That makes sense. Thank you Jeremy!
Do the gnat-riscv64-elf* releases only compile for 64-bit riscv? I think I am confused because I see references to 32-bit versions of the riscv ie.
Would
gnat-riscv64-elf-linux64-12.2.0-1/bin/riscv64-elf-gcc
also compile for a 32-bitrv32imac
architecture given the correct compiler flags? If not, can a gnat-riscv32-elf release be made available that would support that?