Get deep `fsl,enable-lpsr` sleep working

[alistair23]

There is a work in progress branch to add deep sleep support to the 5.4 kernel.

The problem is that deep sleep (called lpsr) doesn't work. The device will go into the deep sleep but I can't get it to wake up.

With lpsr disabled sleep/wake via the physical button work, but automatic sleep doesn't as automatic sleep appears to use lpsr. So I have disabled automatic sleep in Oxide and I have no issues.

This issue is tracking adding support for lpsr and hopefully that fixes the automatic sleep in Oxide and other apps.

[alistair23]

@boxfire

[boxfire]

Well I am sure there is just a missing step. Likely step 2 last bullet from the IMX Reference manual p. 44:

The i.MX 6 and i.MX 7 power management driver maps the low-power modes to the kernel power management states as listed below:

• Standby-maps to STOP mode, which offers significant power saving, as all blocks in the system are put into a low-power state, except for Arm® core, which is still powered on, and memory is placed in self-refresh mode to retain its contents.
• Mem (suspend to RAM) maps to DORMANT mode, which offers most significant power saving, as all blocks in the system are put into a low-power state, except for memory, which is placed in self-refresh mode to retain its contents. If there is"fsl,enable-lpsr" defined in DTB ocrams node, mem is mapped to LPSR mode instead of DORMANT, and all the blocks inthe system are put into power off state, except the LPSR, SNVS, and DRAM power domains.
• System idle maps to WAIT mode.
• If Arm Cortex®-M4 processor is alive together with Arm Cortex-A processor before the kernel enters standby/mem mode,and if Arm Cortex-M4 processor is not in its low-power idle mode, Arm Cortex-A processor triggers the SOC to enter WAIT mode instead of STOP mode to make sure that Arm Cortex-M4 processor can continue running.

The i.MX 6 and i.MX 7 power management driver performs the following steps to enter and exit low power mode:

1. Allow the Cortex-A platform to issue a deep sleep mode request.
2. If STOP or DORMANT mode:
   • Program i.MX 6 CCM_CLPCR or i.MX 7 GPC_LPCR_A7_BSC and GPC_SLPCR registers to set low-power control register.
   • If DORMANT mode, request switching off CPU power when pdn_req is asserted.
   • Request switching off embedded memory peripheral power when pdn_req is asserted.
   • Program GPC mask register to unmask wakeup interrupts.
3. Call cpu_do_idle to execute WFI pending instructions for wait mode.
4. Execute imx6_suspend or imx7_suspend in IRAM.
5. In DORMANT mode, save Arm context, and change the drive strength of DDR PADs as "low" to minimize the power leakage in DDR PADs. Execute WFI pending instructions for stop mode.
6. Generate a wakeup interrupt and exit low-power mode. In DORMANT mode, restore Arm core and DDR drive strength.

In DORMANT mode, the i.MX 6 and i.MX 7 can assert the PMIC_STBY_REQ pin to the PMIC and request a voltage change.The U-Boot or Machine-Specific Layer (MSL) usually sets the standby voltage in STOP mode according to i.MX 6 and i.MX 7data sheet.

[boxfire]

Associated code for imx7d is in

 * arch/arm/mach-imx/pm-imx7.c
 * arch/arm/mach-imx/suspend-imx7.S
 * arch/arm/mach-imx/cpuidle-imx7d.c
 * arch/arm/mach-imx/imx7d_low_power_idle.

If CONFIG_PM, CONFIG_SUSPEND are on then low power mode should be available from that source code.

So with all of that I might suggest turning on all the debug stuff in the 4.14.78 kernel, perhaps with kernel function tracing, checking out what gets called / taken, and then making sure all of that can happen in the 5.4 kernel. I mean there is probably something obvious like the wakeup interrupt not being programmed correctly, but I can't say easily

[boxfire]

interesting. As a debug stopgap:

echo enabled > /sys/class/tty/ttymxc0/power/wakeup

(replace with appropriate pogo uart once I figure out whats going on there?)

[boxfire]

I wonder if its as simple as hitting that for the power button gpio?