QEMU FreeRTOS

[Konstanty]

Since so much is working these days - I've re-tested QEMU on FreeRTOS again.

I think there are some problems relating to setting portNVIC_SYSTICK_CTRL_REG, specifically the code: portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );

These are defined as memory positions, as below

#define portNVIC_SYSTICK_CTRL_REG           ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
#define portNVIC_SYSTICK_LOAD_REG           ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
#define portNVIC_SYSTICK_CURRENT_VALUE_REG  ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
#define portNVIC_SYSPRI2_REG                ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )

I don't see any of these memory addresses inside the machine model... ?

[Konstanty]

Looks like armv7m_nvic.c:517 has something to do with this.

[MattDsouza]

NVIC is the interrupt controller, used by the systick in FreeRTOS - could this be a timer interrupt problem?

[alistair23]

So I can see the read/write addresses for some of these registers. Looking at armv7m_nvic.c:288 I can see the first three of the registers you mention above, but not the fourth (portNVIC_SYSPRI2_REG) Is that the one causing the issue?

[Konstanty]

I've now got a minimal example which crashes QEMU. I guess the debug_printf, and Delay isn't standard - but they are not necessary.

It actually crashes on reading the variable 'end', but not on 'start'. QEMU itself exits with "Floating point exception(core dumped)". I am of course assuming that this works fine on a 'real' netduino/ np2

    // Systick regs
    int *STCSR = (int *)0xE000E010;
    int *STRVR = (int *)0xE000E014;
    int *STCVR = (int *)0xE000E018;

    // Configure Systick   
    *STRVR = 0xFFFFFF;  // max count
    *STCVR = 0;         // force a re-load of the counter value register
    *STCSR = 5;         // enable FCLK count without interrupt

    int start = *STCVR;
    Delay(1000);
    int end = *STCVR;
    debug_printf("%d\n", (end - start - 2));

[Konstanty]

OK, the variable system_clock_scale is zero. Inside the stelaris board definition, they set it to non zero values.

So this definitely is something that needs to be done for the np2.

[alistair23]

Yeah, you are right. Any idea what it should be set to?

[alistair23]

Ok, so I started looking into it. I think it should be set to 18.75GHz for the Netduino Plus 2. If you look in the data sheet section 12.1.2: "The SysTick calibration value is fixed to 18750, which gives a reference time base of 1 ms with the SysTick clock set to 18.75 MHz (HCLK/8, with HCLK set to 150 MHz)."

So by adding system_clock_scale = 19; to netduinoplus2_init() it should fix the issue. I'll push the fix now.

Running the example code you have above I see -2 returned, as systick.tick isn't being incremented. Is that right?