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amadornes / SCM-Localization-Issues

Localization and issues for Super Circuit Maker
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[BUG] Custom Logic Gate Combination with Unexpected Result #333

Closed DoraTheExploder closed 7 years ago

DoraTheExploder commented 7 years ago

I have attempted to replicate a combination of an XOR, NOT, and AND gates in a specific pattern to create a circuit with the truth table below. However, there seems to be some unexpected behavior occuring when Input Y is toggled off, it has a one tick pulse on the Output which should not, as far as I can tell, be occuring. I have recreated this circuit using Vanilla Redstone mechanics as well as a combination of EnderIO Redstone Conduit w/ Project Red Gates and both of those tests work as expected. I have included a link to the scm export below.

X Y OUTPUT
0 0 0
0 1 0
1 0 1
1 1 0

[Blueprint] (https://gist.github.com/1e0aa1c4b3ce9626560e7641ac50202f)

DoraTheExploder commented 7 years ago

I am not absolutely certain that this is the proper location for this post, if it is not, let me know and I will fix the issue.

dokranke commented 7 years ago

Each component has a 1 tick delay, but torches need 2 ticks to process (in vanilla also only one). This is why your circuit doesn't work as expected... Use a subtractor connected to a high signal (torch or constant on 255) instead.