Closed jfng closed 4 years ago
Merging #7 into master will decrease coverage by
0.4%
. The diff coverage is97.8%
.
@@ Coverage Diff @@
## master #7 +/- ##
==========================================
- Coverage 100% 99.59% -0.41%
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Files 4 4
Lines 436 493 +57
Branches 95 107 +12
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+ Hits 436 491 +55
- Misses 0 1 +1
- Partials 0 1 +1
Impacted Files | Coverage Δ | |
---|---|---|
nmigen_soc/csr/bus.py | 100% <100%> (ø) |
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nmigen_soc/csr/wishbone.py | 100% <100%> (ø) |
:arrow_up: |
nmigen_soc/wishbone/bus.py | 98.52% <96.15%> (-1.48%) |
:arrow_down: |
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I've cherry-picked 7f27d90e66fcede136caaeeb6a1d3f76a115ca16 since it's just what we discussed and it seems correct.
For the other commit, could you explain why you made the memory map externally assignable, rather than created by the parent object?
I've cherry-picked 7f27d90 since it's just what we discussed and it seems correct.
Thanks !
For the other commit, could you explain why you made the memory map externally assignable, rather than created by the parent object?
Let's consider the case where the MemoryMap
is created by its parent bus interface. The memory map is extendable, and the bus interface is owned by e.g. a multiplexer. The following happens:
extend=True
extend=True
addr_width
increasesWe have a problem: the updated addr_width
value is now different than the one used to shape the record fields of the bus interface.
A solution is to lazily create the bus interface, only when it is requested from the multiplexer. It would then have up-to-date record fields. The memory map is freezed at the same time.
In order to do this, the memory map has to be created by the multiplexer before the bus interface. The multiplexer adds resources to the map, and uses it to create the bus interface, once requested.
I favored external assignation over passing the memory map to __init__
, because creating a memory map beforehand is not always desirable (e.g. if the interface is tied to a bus initiator, it doesn't need one).
Thanks for the explanation. I agree there is no better way to do this. Please amend the commit to include the rationale, and feel free to merge it once it's done.
This PR adds support for extending the address space of a
MemoryMap
, after it has been instantiated.Use case
Before this PR, the
addr_width
parameter of acsr.Multiplexer
would be the definitive address width of its underlying memory map.This is inconvenient, because it forces the user to be aware of the size and address of each
csr.Element
that will be added to the multiplexer upfront.This PR allows the address space covered by the
csr.Multiplexer
to be extended as resources are added to it.The following primitives can support this use case:
csr.Multiplexer
csr.Decoder
wishbone.Decoder
Contents
nmigen_soc.memory
nmigen_soc.csr
andnmigen_soc.wishbone
to the updated API