Open jfng opened 3 years ago
Why not add the constraint to the appropriate signal depending on the direction?
Why not add the constraint to the appropriate signal depending on the direction?
That is actually the workaround I used when I encountered this.
The issue is that on e.g. Xilinx platforms, this ends up as a create_clock
constraint, which is inaccurate according to UG835 (p. 239):
I don't know whether although inaccurate, it would still be better than no constraint at all.
I see. I'd need to take a closer look for this.
Repro:
Output:
Currently, only two nmigen-boards platforms are affected (arty_a7 and nexys4ddr).
I'm not sure how to approach this:
ResourceManager.request()
encounters one. While not ideal, I think it's still better than preventing the design from building.