Open tilk opened 1 year ago
It was the intended behavior originally. However, I have some plans for a new Verilog/RTLIL backend, which would reuse identical subexpressions. There is no ETA on that.
We have implemented the new IR. However, due to various compatibility reasons, the duplication still happens. It will likely be deduplicated by Amaranth 0.7.
Take the following Amaranth code:
It generates the following Verilog (comments removed for readability):
Notice that the single assignment
v = self.i + self.i
translated to two Verilog assign statementsassign \$2 = i + i;
andassign \$4 = i + i;
.I understand that this is the consequence of treating Amaranth ASTs as trees (as opposed to DAGs, directed acyclic graphs). But this behavior might be unexpected for many Amaranth users, and lead to unexpected performance loss in some situations. (Here, Yosys is able to de-duplicate the expression; this might not work in general). Is this the intended behavior, or a bug?