module ports in generated verilog doesn't have names

I tried to run the sample code found in the getting start part of the documentation.

from amaranth import *
from amaranth.back import verilog

class UpCounter(Elaboratable):
    """
    A 16-bit up counter with a fixed limit.

    Parameters
    ----------
    limit : int
        The value at which the counter overflows.

    Attributes
    ----------
    en : Signal, in
        The counter is incremented if ``en`` is asserted, and retains
        its value otherwise.
    ovf : Signal, out
        ``ovf`` is asserted when the counter reaches its limit.
    """

    def __init__(self, limit):
        self.limit = limit

        # Ports
        self.en = Signal()
        self.ovf = Signal()

        # State
        self.count = Signal(16)

    def elaborate(self, platform):
        m = Module()

        m.d.comb += self.ovf.eq(self.count == self.limit)

        with m.If(self.en):
            with m.If(self.ovf):
                m.d.sync += self.count.eq(0)
            with m.Else():
                m.d.sync += self.count.eq(self.count + 1)

        return m

top = UpCounter(25)
with open("up_counter.v", "w") as f:
    f.write(verilog.convert(top, ports=[top.en, top.ovf]))

As you can see, the ports in the generated verilog have garbage name:

/* Generated by Yosys 0.25 (git sha1 e02b7f64bc7, gcc 13.1.1 -march=x86-64 -mtune=generic -O2 -fno-plt -fexceptions -fstack-clash-protection -fcf-protection -ffile-prefix-map=/build/yosys/src=/usr/src/debug/yosys -fPIC -Os) */

(* \amaranth.hierarchy  = "top" *)
(* top =  1  *)
(* generator = "Amaranth" *)
module top(\$2 , clk, rst, \$1 );
  reg \$auto$verilog_backend.cc:2083:dump_module$2  = 0;
  (* src = "/home/jtremesay/projects/kfpgafactory/sandbox/up_counter.py:27" *)
  input \$1 ;
  wire \$1 ;
  (* src = "/home/jtremesay/projects/kfpgafactory/sandbox/up_counter.py:28" *)
  output \$2 ;
  wire \$2 ;
  (* src = "/home/jtremesay/projects/kfpgafactory/sandbox/up_counter.py:31" *)
  reg [15:0] \$3  = 16'h0000;
  (* src = "/home/jtremesay/projects/kfpgafactory/sandbox/up_counter.py:31" *)
  reg [15:0] \$3$next ;
  (* src = "/home/jtremesay/projects/kfpgafactory/sandbox/up_counter.py:36" *)
  wire \$4 ;
  (* src = "/home/jtremesay/projects/kfpgafactory/sandbox/up_counter.py:42" *)
  wire [16:0] \$6 ;
  (* src = "/home/jtremesay/projects/kfpgafactory/sandbox/up_counter.py:42" *)
  wire [16:0] \$7 ;
  (* src = "/home/jtremesay/projects/kfpgafactory/.direnv/python-3.11/lib/python3.11/site-packages/amaranth/hdl/ir.py:527" *)
  input clk;
  wire clk;
  (* src = "/home/jtremesay/projects/kfpgafactory/.direnv/python-3.11/lib/python3.11/site-packages/amaranth/hdl/ir.py:527" *)
  input rst;
  wire rst;
  assign \$4  = \$3  == (* src = "/home/jtremesay/projects/kfpgafactory/sandbox/up_counter.py:36" *) 5'h19;
  assign \$7  = \$3  + (* src = "/home/jtremesay/projects/kfpgafactory/sandbox/up_counter.py:42" *) 1'h1;
  always @(posedge clk)
    \$3  <= \$3$next ;
  always @* begin
    if (\$auto$verilog_backend.cc:2083:dump_module$2 ) begin end
    \$3$next  = \$3 ;
    (* src = "/home/jtremesay/projects/kfpgafactory/sandbox/up_counter.py:38" *)
    casez (\$1 )
      /* src = "/home/jtremesay/projects/kfpgafactory/sandbox/up_counter.py:38" */
      1'h1:
          (* full_case = 32'd1 *)
          (* src = "/home/jtremesay/projects/kfpgafactory/sandbox/up_counter.py:39" *)
          casez (\$2 )
            /* src = "/home/jtremesay/projects/kfpgafactory/sandbox/up_counter.py:39" */
            1'h1:
                \$3$next  = 16'h0000;
            /* src = "/home/jtremesay/projects/kfpgafactory/sandbox/up_counter.py:41" */
            default:
                \$3$next  = \$7 [15:0];
          endcase
    endcase
    (* src = "/home/jtremesay/projects/kfpgafactory/.direnv/python-3.11/lib/python3.11/site-packages/amaranth/hdl/xfrm.py:519" *)
    casez (rst)
      1'h1:
          \$3$next  = 16'h0000;
    endcase
  end
  assign \$6  = \$7 ;
  assign \$2  = \$4 ;
endmodule

Based on what I see in the documentation, I expected the ports to have real names:

module top(clk, rst, en, ovf);

I have installed amaranth with pip: pip install -U amaranth[builtin-yosys].

$ pip freeze | grep amaranth
amaranth==0.3
amaranth-yosys==0.25.0.0.post74

amaranth-lang / amaranth

module ports in generated verilog doesn't have names #867