Read Verilog pinlist

[drom]

Do you plan to generate a wrapper for the arbitrary verilog module? I have started this pinlist reader library https://github.com/drom/verilog-pinlist It uses this Verilog parser https://github.com/tree-sitter/tree-sitter-verilog Will it be useful?

[ameetgohil]

yes, absolutely. right now, i'm using ben's script to get all the pins and generate the wrapper with templates

[ameetgohil]

@drom Is the pinslist reader library ready to use?

[drom]

I still fixing some bugs, but you can try using it. I have added instruction in the README.md file https://github.com/drom/verilog-pinlist

[ameetgohil]

Verilator generates a header file called Vtop.h with has signal width, direction, name which are easily extracted using regex. Here's the regex i used: /VL_([^\(]*)\(([^\,\)]*),([^\D]*),([^\D]*)/g This way i don't have to worry about parameters or defines b/c verilator figures all that out.
See https://github.com/ameetgohil/signalflip-js/blob/master/src/GenerateWrapper.js

[drom]

Could you create node bindings, that would wrap any verialted module and then discover pinlist dynamically?

[ameetgohil]

Yes, that's definitely feasible. I'll get on that this week