amichai-bd / rvc_asap

riscv-core-as-simple-as-passible
MIT License
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Details inside #80

Closed gilyaakov closed 2 years ago

gilyaakov commented 2 years ago

Add defines to the addresses in tests, embed the script of .sv->.mif in build (there are couple things we need to fix in it). Furthermore made a FPGA IO test and made complete compilation and synthesis (also fixed the memory sizes).

We are on FPGA!!!