Race condition w.r.t. reset

[tudortimi]

Since the UVC doesn't do any kind of reset at the start of the simulation (only when triggered), I need to implement drive a negedge on reset_n at time 0:

  bit reset_n = 1;
  bit clk;

  always #1 clk = ~clk;

  initial begin
    reset_n <= 0;
    @(negedge clk);
    @(negedge clk);
    reset_n <= 1;
  end

Normally I start a sequence in my test also at time 0:

virtual task run_phase(uvm_phase phase);
    apb_filter_tb::filter_sequence seq =
      apb_filter_tb::filter_sequence::type_id::create("seq", this);

    phase.raise_objection(this);

    seq.start(tb_env.master_agent.sequencer);

    phase.drop_objection(this);
  endtask

The problem is that there is a race condition here and the sequence process gets killed. This is because the sequencer's handle_reset() method stops all running sequences.

[amiq-consulting]

Why would you start the sequence at time 0?