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amiq-consulting / image-upscaling-CNN

How to Accelerate an Image Upscaling CNN on FPGA Using HLS
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Some problems I meet #1

Open JacoboJin opened 2 years ago

JacoboJin commented 2 years ago

Hi! I meet some problems.

WARNING: [HLS 200-885] Unable to schedule 'load' operation ('Val2') on array 'buffer_data_V' due to limited memory ports. Please consider using a memory core with more ports or partitioning the array 'buffer_data_V'. Resolution: For help on HLS 200-885 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-885.html WARNING: [HLS 200-960] Cannot flatten loop 'VITIS_LOOP_34_1' (C:/Users/ZhenJie/Desktop/image-upscaling-CNN-main/image-upscaling-CNN-main/Bicubic-Interpolation/Accelerated-Bicubic-Interpolation/Vivado-HLS-Source-Code/bicubic.cpp:33:9) in function 'bicubic' more than one sub loop. Resolution: For help on HLS 200-960 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-960.html

When I ran your bicubic code on Vitis HLS platform, I have found that the Latency of the code is too large to "2711064"so that I can not have a good method to solve it. Could you tell me how you solve this problem?

GinnaVamshiKrishna commented 1 year ago

Hello. We’re you able to successfully generate this project on vitis HLS?

GinnaVamshiKrishna commented 1 year ago

Were you able to successfully implement it in vitis HLS?

Manashpratimhazarika commented 3 months ago

I have executed the code in Vivado HLS 2019.1 for Zynq ZCU104 FPGA Board but it gives the following simulation error FSRCNN error

INFO: [SIM 2] CSIM start INFO: [SIM 4] CSIM will launch GCC as the compiler. make: 'csim.exe' is up to date. ERR: [SIM 100] CSim failed with errors. INFO: [SIM 3] CSIM finish

Can you help me in this regard manashpratimhazarika6@gmail.com