Open m-ou-se opened 4 years ago
An alternative idea is to invert the REQ logic to idle low, which would simplify the hardware and maybe reduce the mental overhead a bit...?
Truth table:
DEV ARB DEV DEV
1:REQ 1:REQ/nGO -> 1:nGO GATES
LOW In: HiZ -> HI OFF Idle/Waiting for request
HI In: HiZ/Out: HI -> HI OFF Request to send/Not accepted
HI Out: LOW -> LOW ON Request accepted
Notes:
U1: XNOR gate (i.e. SN74HC266 or CD4077)
U2: Tristate buffer (i.e. SN74LVC125)
C1: sized to avoid false nGO
triggers, depending on capacitive load
The nCS
, COPI
and SCK
tristate buffer gates were omitted in the drawing for brevity (read "lazyness").
EDIT: Updated drawing with correct logic gate, added C1
for de-glitching, added R2
for defined behaviour when the device is not plugged in. nCS
driven from controller, through tristate gating buffer.
That wouldn't work: With this AND port, the nGO
pin would be low whenever the REQ
is low. Meaning the communication is enabled while the device isn't even asking to communicate.
In my schematic, I tried to minimize both the number of pins that have to go the device (the lines that cross the leftmost blue line: just one go/req line next to the three spi lines), and the amount of extra components needed on the device (just one resistor).
No 1:REQ/nGO
is in floating state, so both ports will be low, so the AND XNOR output / nGO
input is HI...
Only when the arbitrator's 1:REQ/nGO
is pulled low and the device's 1:REQ
is hi nGO
will go low
in floating state
How could that work? How would the arbitrator tell if there's an incoming request if the pin is floating? It'll just randomly measure high or low if that pin is floating. Same for the nCS pin.
In idle state it will be pulled low by 1:REQ
, but yeah true that nCS
will be a problem as is...
But if REQ is low in idle, the output of the AND port will be low, enabling the buffer and enabling the GO signal.
Oh sorry, i meant it should be an XNOR gate
Just some idea: With a few resistors, transistors, and a diode, it would be possible to use a single GPIO pin on the arbitrator to get a transfer request from a device, and accept that request using the same pin, while also controlling the buffer enable line and the chip select of the arbitrator: