Open StancaPop opened 1 year ago
@StancaPop Is there a reason the testing isn't catching this issue? Can you verify its setting this port in the test model?
Tested with Vivado versions 2021.1 (BOOT.BIN generation did not work) and 2019.1 (BOOT.BIN generation worked), both resulted in generating a .bit file. Without the modification, the project cannot be built.
This issue still should be caught by CI. But that's not happening due to this condition https://github.com/analogdevicesinc/TransceiverToolbox/blob/21621207c7de44b2b9458246601e5beba2105fac/test/setportmapping.m#L76
Need to better understand what the DAC validIn really does
The fifo_rd_en port of the util_dac_1_upack was already driven by axi_adrv9001/dac_1_valid_i0 and it generated an error in the HWA when trying to connect it to the IP Load Tx Data OUT port of the HDL_DUT_IP.
This fix deletes the net in the preprocessing script and fixes the error.