ADRV9001 Clock domain crossing between Tx and Rx

IstvanZsSzekely commented 1 year ago

The test setup used Vivado version 2019.1. In case a different version is used:

export ADI_IGNORE_VERSION_CHECK=TRUE Build steps that may be different:
make -C .CI/scripts build HDL_BRANCH=hdl_2019_r1
At step 1.2 choose the reference design that will be tested, as well as the fast-slow clock ratio
When testing on the hardware, make sure that the clocks in the profile is set according to the fast-slow clock ratio In order to check if the synchronizers are created, take a look at the created Vivado design, and look for sync_input and output. When only Tx or Rx is used, the synchronizers will still be present, but the IPs will be replaced by wires (bypass mode).

tfcollins commented 1 year ago

Preprocessing adrv9001 zcu102 rxtx
cp: cannot stat '../../../../../hdl/vendor/AnalogDevices/vivado/quiet.mk': No such file or directory
INFO: [Common 17-206] Exiting Vivado at Thu May  4 14:52:50 2023...
### Generated logfile: <a href="matlab:edit('/jenkins/workspace/TransceiverToolbox_PR-141@2/test/tp7427ac2d_b8ae_48d9_87c0_42737ed3460a/hdlsrc/testModel_regs/workflow_task_CreateProject.log')">/jenkins/workspace/TransceiverToolbox_PR-141@2/test/tp7427ac2d_b8ae_48d9_87c0_42737ed3460a/hdlsrc/testModel_regs/workflow_task_CreateProject.log</a>
Build error: ADRV9002 ZCU102 (RX & TX - RX IS FASTER OR HAS PRIORITY)
  MException with properties:

    identifier: 'hdlcommon:workflow:WorkflowStageError'
       message: 'Task "Create Project" unsuccessful. See log for details.'
         cause: {}
         stack: [39x1 struct]
    Correction: []

Task "Create Project" unsuccessful. See log for details.
  39x1 struct array with fields:

    file
    name
    line

master branch now uses hdl_2021_r1 so my guess is that there might be some port renamings necessary

IstvanZsSzekely commented 1 year ago

Preprocessing adrv9001 zcu102 rxtx
cp: cannot stat '../../../../../hdl/vendor/AnalogDevices/vivado/quiet.mk': No such file or directory
INFO: [Common 17-206] Exiting Vivado at Thu May  4 14:52:50 2023...
### Generated logfile: <a href="matlab:edit('/jenkins/workspace/TransceiverToolbox_PR-141@2/test/tp7427ac2d_b8ae_48d9_87c0_42737ed3460a/hdlsrc/testModel_regs/workflow_task_CreateProject.log')">/jenkins/workspace/TransceiverToolbox_PR-141@2/test/tp7427ac2d_b8ae_48d9_87c0_42737ed3460a/hdlsrc/testModel_regs/workflow_task_CreateProject.log</a>
Build error: ADRV9002 ZCU102 (RX & TX - RX IS FASTER OR HAS PRIORITY)
  MException with properties:

    identifier: 'hdlcommon:workflow:WorkflowStageError'
       message: 'Task "Create Project" unsuccessful. See log for details.'
         cause: {}
         stack: [39x1 struct]
    Correction: []

Task "Create Project" unsuccessful. See log for details.
  39x1 struct array with fields:

    file
    name
    line

master branch now uses hdl_2021_r1 so my guess is that there might be some port renamings necessary

hdl_2021_r1 and hdl_2019_r1 had a couple of reference design differences, which will be fixed for hdl_2021_r1. hdl_2019_r1 will not work with the upcoming commit

IstvanZsSzekely commented 1 year ago

 Writing bitstream ./system_top.bit...
 INFO: [Vivado 12-1842] Bitgen Completed Successfully.
 INFO: [Common 17-83] Releasing license: Implementation
 68 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
 write_bitstream completed successfully
 write_bitstream: Time (s): cpu = 00:00:38 ; elapsed = 00:00:36 . Memory (MB): peak = 7520.711 ; gain = 0.000 ; free physical = 10686 ; free virtual = 101645
 INFO: [Common 17-206] Exiting Vivado at Fri May  5 11:48:14 2023...
 [Fri May  5 11:48:20 2023] impl_1 finished
 wait_on_run: Time (s): cpu = 00:00:01 ; elapsed = 00:12:58 . Memory (MB): peak = 3149.172 ; gain = 0.000 ; free physical = 11711 ; free virtual = 102667
 error copying "vivado_prj.runs/impl_1/system_top.sysdef": no such file or directory
     while executing
 "file copy -force vivado_prj.runs/impl_1/system_top.sysdef $sdk_loc/system_top.hdf"
     (file "vivado_build.tcl" line 45)
INFO: [Common 17-206] Exiting Vivado at Fri May  5 11:48:20 2023...

There is an issue with BOOT.BIN generation with version 2021.1, working on a solution

IstvanZsSzekely commented 1 year ago

PR successfully built for Vivado version 2019.1 on the Jenkins server.

analogdevicesinc / TransceiverToolbox

ADRV9001 Clock domain crossing between Tx and Rx #141