Understanding the 'Donut Hole'

[Beauxrel]

The FMCOMMS User guide claims "All the Analog Devices Vivado HDL reference designs have inside a ‘donut hole’ to accommodate custom IPs."

My team wants to know if we would be okay just using Vitis Model Composer to design our Mod/Demod chain and have the reference design pass data through axi to that or using HDL-Coder + all the other packages that are required (Very expensive route).

Sell me on these IPs that I can connect to the reference design, would I be able to create a QAM-16 Demod in verilog that the reference design will send IQ data to and use that somewhere else in my system?

[Beauxrel]

@tfcollins When I copied the ZCU102 plugin_rd.m file this clkwiz interface was in there. - Is the workflow prompting me to make this decision because of that file? or

• Can I take this out and keep my reference design running at 300MHz?

[tfcollins]

When MATLAB inserts IP it needs to give it a clock. This is used for the data and the control (AXI-LITE) interface. This is required to my knowledge

[Beauxrel]

@tfcollins This one signal is giving me issues, if I have axi stream set for the dma, I get this error.

connect_bd_intf_net -intf_net util_ad9361_adc_pack_packed_fifo_wr [get_bd_intf_pins axi_ad9361_adc_dma/fifo_wr] [get_bd_intf_pins util_ad9361_adc_pack..."

The problem being if I am streaming I cant have the fifo interface

% DMA Ready signal
hRD.addInternalIOInterface( ...
    'InterfaceID',    'DMA Ready', ...
    'InterfaceType',  'IN', ...
    'PortName',       'dma_rdy', ...
    'PortWidth',      1, ...
    'InterfaceConnection', 'axi_ad9361_adc_dma/s_axis_ready', ...
    'IsRequired',     false);

This all stems from setting this in the workflow advisor. Which to my knowledge is needed