Open Beauxrel opened 10 months ago
Cannot find this signal in the reference design for 2021.1 should it be util_ad9361_dac_fifo/din_valid_in_0 ?
hRD.addInternalIOInterface( ... 'InterfaceID', 'IP Load Tx Data OUT', ... 'InterfaceType', 'OUT', ... 'PortName', 'util_dac_unpack_dac_valid_00', ... 'PortWidth', 1, ... 'InterfaceConnection', 'util_ad9361_dac_upack/din_valid_in_0', ... 'IsRequired', false);
Cannot find this signal in the reference design for 2021.1 should it be util_ad9361_dac_fifo/din_valid_in_0 ?
hRD.addInternalIOInterface( ... 'InterfaceID', 'IP Load Tx Data OUT', ... 'InterfaceType', 'OUT', ... 'PortName', 'util_dac_unpack_dac_valid_00', ... 'PortWidth', 1, ... 'InterfaceConnection', 'util_ad9361_dac_upack/din_valid_in_0', ... 'IsRequired', false);