In I2cMWrCfg and I2cMRdCfg the address registers are incorrectly set for 10-bit addressing mode:
The addressing mode is determined based on the device address: 7-bit mode for addresses up to 255 and 10-bit mode otherwise. However, this assumes that for example address 50 is a 7-bit address. This is not always the case. The 7-bit address 50 is a different address than the 10-bit address 50.
Due to the masking and shifting operations in I2cMWrCfg, at most 9 of the 10 address bits are actually used.
In I2cMRdCfg, bit 0 of ADDR1 is always set, which is incorrect for 10-bit addressing mode.
In
I2cMWrCfgandI2cMRdCfgthe address registers are incorrectly set for 10-bit addressing mode:I2cMWrCfg, at most 9 of the 10 address bits are actually used.I2cMRdCfg, bit 0 of ADDR1 is always set, which is incorrect for 10-bit addressing mode.