Bode plot CHB mode issue

[SoCalIRL]

ALICE Desktop 1.3 (28th April 2020) WIN7PRO-64

When running a frequency sweep, CHB mode switches from Hi-Z to Split I/O the moment the Run button is pressed. It can be switched back without interrupting the run but does invalidate if if this is not done.

[damercer]

No, It is done that way by design. CH B has to be in Split I/O mode because it is assumed to be an input on BIN pin (measuring output response of circuit under test).

Are you using on older Rev D version of M1lK?

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[External]

ALICE Desktop 1.3 (28th April 2020) WIN7PRO-64

When running a frequency sweep, CHB mode switches from Hi-Z to Split I/O the moment the Run button is pressed. It can be switched back without interrupting the run but does invalidate if if this is not done.

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[SoCalIRL]

Thanks for the quick response Damercer, and for clearing that point up.

I'm using the rev.F board so I do have the 8-pin header not the older 6-pin.

I'm not sure that the behaviour you outline is appropriate as a default mode of operation however. Once the characteristic is known it isn't a big deal, but it does add a layer of abstraction which is undesirable in early stage learning - especially as there is a significant difference in channel impedance between the modes (as illustrated below).

For the sake of providing some context, I'm working through the materials in the Circuits 1 activities resource to gain some insight into the potential for the system to support teaching activities in a remote setting. This particular observation was made whilst working through the 'Frequency compensated voltage divider' exercise here.

This case is somewhat atypical as it employs the intrinsic characteristics of BIN as the lower half of the circuit and it is the differing nature of the Split I/O and Hi-Z circuits which has lead to the query.

In any case, as I understand it, whilst the point of the Split I/O mode is that the CHB and BIN functions are isolated from each other, meaning that in principle at least, this mode of operation should behave in a similar fashion to Hi-Z for any signal connected to BIN; this is not the case here and there is a clear and significant difference in the capacitance between the modes. Compounding the matter is a seperate issue whereby the AWG mode displayed is not updated when this change from Hi-Z to SVMI Split I/O is made, and continues to display the previous mode. The top image below shows the AWG panel as displayed after Run is pressed, the lower image reveals the actual channel configuration at that time.

Returning to the point of the differing behaviours, I have attached screen captures of the 3 relevant CHB mode combinations (SVMI Split I/O, Hi-Z Split I/O, and Hi-Z) in two circuit configurations (Pure resistive 1MOhm input and RC input with ~280pF capacitance in parallel).

01: Initial run after activating Bode window CHB circuit in Hi-Z mode has earlier been characterised and found to have a capacitance of ~350pF; 1MOhm channel resistance is a given. Input circuit consists of ~280pF in parallel with 1MOhm (350pF not reasonably achievable with ADALP2000 kit components) CHB is in Split I/O mode CHB scope trace exhibits sinusoidal noise, observable here as an artifact centered at 1kHz and, I expect, linked to the output frequency of CHB in this mode (see first image above for CHB set point). Connection is to BIN Result suggests over compensation where slight under compensation is expected

02: No parallel capacitance CHB is in SVMI Split I/O mode CHB scope trace exibits sinusoidal noise Connection is to BIN Result is, naturally, under compensated

03: No parallel capacitance CHB is in Hi-Z mode No sinusoidal noise apparent on CHB scope trace Connection is to BIN Increase in dropoff with frequency aligns with higher channel capacitance in this mode

04: No parallel capacitance CHB is in Hi-Z Split I/O mode CHB scope trace exibits sinusoidal noise Connection is to BIN Identical to 02

05: ~280pF parallel capacitance reinstated CHB is in Hi-Z mode No sinusoidal noise apparent on CHB scope trace Connection is to BIN Result is slightly under compensated which is as expected

Attached images 06 and 07 illustrate the significance of the noise induced by activation of the Split I/O mode.

So, in concluding, and in the context of this specific type of exercise, were the initial characterisation performed on BIN in Split mode, and were the output setting for CHB configured for to DC, then this method of operation can be accommodated tolerably well. However this still introduces several unnecessary convolutions to a learning program which only serve to clutter then environment and detract focus from the main points.

[damercer]

The parasitics associated with the the CHA/B and A/BIN pins are what they are and I can't hide that fact from the user in the software. There is another underlying reason due to hardware/firmware realities that make it necessary to use SPLIT I/O mode on BIN while doing Bode plots. To extend the sweep range to the highest frequencies possible the AWG A channel's sample rate is doubled to 200 KSPS which means both output data streams (at 100 KSPS each) feed the CHA DAC and the CHB DAC has to also be in SVMI mode outputing a (random) DC level.

We are in the process of developing a range of m1k accessory boards. One or the other of the input buffer boards might be of interest to greatly reduce the input capacitance. We will not be selling manufactured boards, only offering the CAD files so users can order boards from their favorite board prototyping web site.

https://github.com/analogdevicesinc/education_tools/tree/m1k-accessory-boards/m1k-accessory-boards

[SoCalIRL]

Cheers Doug,

Don't get me wrong, I'm not suggesting that the performance of the system is anything less than incredible for what it is. The limitations in what the system can do are actually part of what makes it interesting as a teaching tool, and are actually a strength in this context. The fact that the frequency dependent divider circuit employs the channel characteristics in the manner it does makes for a great learning exercise.

I've also had a read through the accessory board resources and they too make for some fantastic student exercises.

What prompted this conversation though was the fact that the learning documentation takes the participant through the process of building a frequency compensated divider which is expected to be validated using a square wave signal. The exercise specifically, and reasonably, advises CHB be set to Hi-Z mode.

The sweep is then conducted, however unknown to the participant, the sweep is performed with CHB in SVMI Split I/O mode (the AWG window does not update the operating mode on the display, as mentioned previously). Parasitic capacitance is computed based on this setting and when the participant then builds their compensated divider, and attempts to measure the square wave at the point of division with CHB in Hi-Z mode, overcompensation is observed.

So the issue here isn't anything to do with trying to hide the parasitics (this exercise is actually very specifically benefiting from them), the issue is that the circuit nature is being altered in the background without the participant being informed.

This is a hidden change, and finding it involves having sufficient confidence in your workings, sufficient knowledge of measurement circuit topologies, and sufficient experience dealing with these sorts of interfaces, to know not only that the problem lies with how the ADALM is presenting itself rather than in something that you're doing wrong, but also that that problem is configuration related.

Now naturally, if this hardware does move forward to adoption, this can be accounted for in the teaching plan by simply specifying the SVMI Split I/O mode throughout, and simply ignoring the Hi-Z option. Now that I'm aware of the change and the reasoning for it and this is absolutely fine, however it would still be beneficial if the AWG window updated to reflect the mode change for the avoidance of such confusions in any other circumstance.

[damercer]

This is not the right forum for this sort of discussion. This is the place to mainly report software bugs or suggest enhancements.

It appears that your concerns are more focused on the course materials on the Analog Devices Wiki.

The best place to bring up issues on the Wiki content is on the ADI Engineer Zone in the Virtual Classroom section. The actual people who maintain the teaching materials will see it there.

https://ez.analog.com/adieducation/university-program

Alternatively, if you are inclined to contribute to the content on the ADI Wiki you might consider signing in to the Wiki with your MyAnalog account and making changes to the teaching materials pages. Non ADI users can make changes ( maybe only to text, not sure if they can upload new media content ) and save but only employees can approve the changes for public view.

Anyway thanks for the feedback.

[SoCalIRL]

Thanks Doug, I'll take any points on the teaching materials over to that forum so.

I would however maintain that the fact the AWG interface does not update the mode of CHB when you click run on the Bode interface is a bug.