analogdevicesinc / hdl

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[BUG] timing Constraints NOT met for adrv9009zu11eg adrv2crr_fmc #1284

Closed ekigwana closed 5 months ago

ekigwana commented 7 months ago

Describe the bug main branch @ e2ca5a991aadff875d54c82e8174ba641dc2fb09 fails to meet timing

To Reproduce Steps to reproduce the behavior:

  1. Clone repository
  2. cd projects/adrv9009zu11eg/adrv2crr_fmc
  3. make clean
  4. make
  5. See error. Build adrv9009zu11eg project [.../projects/adrv9009zu11eg/adrv2crr_fmc/adrv9009zu11eg_vivado.log] FAILED
  6. Open project in vivado
  7. Open implementation
  8. Run Reports -> Timing -> Report Timing
  9. Report Timing Options tab set Number of paths per group to 100 and click 'OK' to generate report

Expected behavior Build with no DDR4 related timing Setup failures.

Screenshots Screenshot_20240306_162332

Desktop (please complete the following information):

Additional context See attached timing report (formart is rpx). adrv9009zu11eg_adrv2ctt_fmc_timing_1.txt

IuliaCMoldovan commented 6 months ago

Hi ekigwana,

Sorry for the delayed reply. I wasn't able to encounter your issue, and I reproduced your setup. For me, the project was successfully built. I also tried with the latest main @ 393a1f6fd6d19aff49511d5473dd258887badf0d and it still builds without timing issues. Have you tried to run make clean-all and then make again? Could you try to get the latest changes from main and run again?

Best regards, Iulia