Add support for AD408X on ZedBoard

[PopPaul2021]

PR Description

This PR adds the following:

• the ad_serdes_in module was modified to allow external reset
• the ad_pack module was modified to allow MSB align
• the up_adc_common exposes the up_adc_ddr_edgesel, up_adc_num_lanes and up_adc_sdr_ddr_n signals
• AXI_AD408X IP
• AXI_AD408X IP documentation
• AD4080 project on ZedBoard
• AD4080 project on ZedBoard documentation

  PR Type

• [ ] Bug fix (change that fixes an issue)
• [x] New feature (change that adds new functionality)
• [ ] Breaking change (has dependencies in other repos or will cause CI to fail)

PR Checklist

• [x] I have followed the code style guidelines
• [x] I have performed a self-review of changes
• [x] I have compiled all hdl projects and libraries affected by this PR
• [x] I have tested in hardware affected projects, at least on relevant boards
• [x] I have commented my code, at least hard-to-understand parts
• [x] I have signed off all commits from this PR
• [x] I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
• [x] I have not introduced new Warnings/Critical Warnings on compilation
• [ ] I have added new hdl testbenches or updated existing ones

[PopPaul2021]

V2: Cosmetics after review.

[PopPaul2021]

V3: After fixing the critical warning and rebase.

[PopPaul2021]

V4: After fixing the CRITICAL WARNING: There are 27 registers with no clocks !!! by defining the clocks in system_constr.xdc and rebase.

[PopPaul2021]

The https://github.com/analogdevicesinc/hdl/pull/1470 and https://github.com/analogdevicesinc/hdl/pull/1469 PRs have to be merged before this one.