Agilex: JESD204C support

bluncan commented 1 month ago

PR Description

Adds JESD204C support for Agilex 7 I-Series (FM87) boards. It uses the Intel F-Tile PMA and FEC Direct PHY IP as the physical layer alongside a custom 64b/66b (RX) and 66b/64b (TX) asynchronous gearbox.

The link layer and transport layer IPs variants for Intel were also updated to account for some missing signals that were not connected or had their widths hard-coded for JESD204B.

Tested on hardware with AD9081 up to 24.75 Gbps with 8 lanes.

Requires Quartus Pro 24.1+

PR Type

[ ] Bug fix (change that fixes an issue)
[x] New feature (change that adds new functionality)
[ ] Breaking change (has dependencies in other repos or will cause CI to fail)

PR Checklist

[x] I have followed the code style guidelines
[x] I have performed a self-review of changes
[x] I have compiled all hdl projects and libraries affected by this PR
[x] I have tested in hardware affected projects, at least on relevant boards
[ ] I have commented my code, at least hard-to-understand parts
[x] I have signed off all commits from this PR
[x] I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
[ ] I have not introduced new Warnings/Critical Warnings on compilation
[ ] I have added new hdl testbenches or updated existing ones

bluncan commented 1 month ago

v2: Fixed guideline check

bluncan commented 1 week ago

v2: Fixed licenses

analogdevicesinc / hdl