Simplifies the interconnect logic, which is now just a set of muxes controlled by a signal from the offload module.
This makes the SYNC instructions optional, and reduces the trigger to first instruction latency.
Since it acts as a substitute for the offload module, axi_ad5766 had to be updated as well in order for it to provide the same interconnect control signal.
(This PR should be merged after https://github.com/analogdevicesinc/hdl/pull/1501)
PR Type
[ ] Bug fix (change that fixes an issue)
[x] New feature (change that adds new functionality)
[ ] Breaking change (has dependencies in other repos or will cause CI to fail)
PR Checklist
[x] I have followed the code style guidelines
[x] I have performed a self-review of changes
[x] I have compiled all hdl projects and libraries affected by this PR
[ ] I have tested in hardware affected projects, at least on relevant boards
[x] I have commented my code, at least hard-to-understand parts
[x] I have signed off all commits from this PR
[ ] I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
[x] I have not introduced new Warnings/Critical Warnings on compilation
[x] I have added new hdl testbenches or updated existing ones
PR Description
Simplifies the interconnect logic, which is now just a set of muxes controlled by a signal from the offload module. This makes the SYNC instructions optional, and reduces the trigger to first instruction latency.
Since it acts as a substitute for the offload module, axi_ad5766 had to be updated as well in order for it to provide the same interconnect control signal. (This PR should be merged after https://github.com/analogdevicesinc/hdl/pull/1501)
PR Type
PR Checklist