unit_level_tb: Revert SV support

IstvanZsSzekely commented 2 weeks ago

PR Description

Added SystemVerilog support breaks some of the current unit level testbenches. Removing support for SystemVerilog, until incompatibilities between Verilog and SystemVerilog are understood and fixed.

PR Type

[x] Bug fix (change that fixes an issue)
[ ] New feature (change that adds new functionality)
[ ] Breaking change (has dependencies in other repos or will cause CI to fail)

PR Checklist

[x] I have followed the code style guidelines
[x] I have performed a self-review of changes
[ ] I have compiled all hdl projects and libraries affected by this PR
[ ] I have tested in hardware affected projects, at least on relevant boards
[ ] I have commented my code, at least hard-to-understand parts
[x] I have signed off all commits from this PR
[ ] I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
[x] I have not introduced new Warnings/Critical Warnings on compilation
[ ] I have added new hdl testbenches or updated existing ones

gastmaier commented 2 weeks ago

do you have a list of the broken ones?

IstvanZsSzekely commented 2 weeks ago

Yes, here are the testbenches that are failing in addition to the ones that were already failing for other reasons: jesd204/axi_jesd204_rx_regmap_tb jesd204/axi_jesd204_tx_regmap_tb jesd204/soft_pcs_pattern_align_tb util_pack/cpack_tb util_pack/underflow_tb util_pack/upack_tb

analogdevicesinc / hdl