common: coraz7s: Add axi_iic_ard for evb eeprom

[gastmaier]

PR Description

Adds an AXI IIC Controller to the common project to be used mostly to read the EVB EEPROM.

    IIC Changes:
    Project       Old          New          IIC Subordinate
    ad4170_asdz   ps-12, 44a4  ps-11, 4416  24AA32A
    ad57xx_ardz   PS7 IIC      ps-11, 4416  24AA32A
    pulsar_adc    none         ps-11, 4416  -
    ad719x_asdz   none         ps-11, 4416  -
    cn0579        ps-12, 44a4  ps-11, 4416  AD5696
    cn0540        ps-12, 44a4  ps-11, 4416  LTC2606
    cn0561        PS7 IIC      ps-11, 4416  M24C02

    IRQ index changes:
    ad4170_asdz
    * $hier_spi_engine 11 -> 12

    ad57xx_ardz
    * ad57xx_dma 12 -> 13
    * $hier_spi_engine 11 -> 12

    cn0579
    * cn0579_dma 13 -> 12
    * axi_iic_ard 12 -> 11

    cn0540
    * $hier_spi_engine 11 -> 12

On linux, some rework to the cora dtsi is required to load the fpga axi as an overlay, since we will defer loading the bitsream moving forward. And existing merged dts?

PR Type

• [ ] Bug fix (change that fixes an issue)
• [X] New feature (change that adds new functionality)
• [x] Breaking change (has dependencies in other repos or will cause CI to fail)

PR Checklist

• [ ] I have followed the code style guidelines
• [ ] I have performed a self-review of changes
• [ ] I have compiled all hdl projects and libraries affected by this PR
• [ ] I have tested in hardware affected projects, at least on relevant boards
• [ ] I have commented my code, at least hard-to-understand parts
• [ ] I have signed off all commits from this PR
• [ ] I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
• [ ] I have not introduced new Warnings/Critical Warnings on compilation
• [ ] I have added new hdl testbenches or updated existing ones