Add Cache Coherency support on Ultrascale projects - Githubissues

analogdevicesinc / hdl

HDL libraries and projects

https://wiki.analog.com/resources/fpga/docs/hdl

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Add Cache Coherency support on Ultrascale projects #1527

Open podgori opened 6 days ago

podgori commented 6 days ago

PR Description

This commit enables Cache Coherency on Ultrascale+ projects, leaving it disabled for the other platforms.

Updated the adi_board.tcl script to automatically select the coherent interface, based on the CACHE_COHERENCY parameter.

PR Type

[ ] Bug fix (change that fixes an issue)
[x] New feature (change that adds new functionality)
[ ] Breaking change (has dependencies in other repos or will cause CI to fail)

PR Checklist

[x] I have followed the code style guidelines
[x] I have performed a self-review of changes
[ ] I have compiled all hdl projects and libraries affected by this PR
[ ] I have tested in hardware affected projects, at least on relevant boards
[x] I have commented my code, at least hard-to-understand parts
[x] I have signed off all commits from this PR
[ ] I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
[ ] I have not introduced new Warnings/Critical Warnings on compilation
[ ] I have added new hdl testbenches or updated existing ones