Remove registers clocked by negative edges in axi_ad9361 dev_if

analogdevicesinc / hdl

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Remove registers clocked by negative edges in axi_ad9361 dev_if #296

Closed gs-jgj closed 5 years ago

gs-jgj commented 5 years ago

These registers don't seem to have any effect given that clk should be the same as l_clk, but instead make it much harder to close timing in high density designs.

Csomi commented 5 years ago

See #297 for more info. Will close this issue when we merged the solution. Thanks!

Csomi commented 5 years ago

See #299 .