Open drorar opened 2 years ago
I've also seen issues with this module. The clock monitor appears to have synchronization registers but doesn't have constraints, or perhaps ASYNC_REG attributes, to tell the tool its an async clock path. For some reason I don't get a timing error, just a critical warning.
Describe the bug Hello
In the AD9361 (Xilinx -- Vivado 2021.2) I get hold time issue between up_d_count and d_count in the up_clock_mon file The d_count is generate in a different clock then the up_d_count
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