[BUG] AD9361 Xilinx axi_ad9361_lvds_if

[AlexLao512]

Seems commit 83d3bded6312449766385730ab07b3afde1adbfe from years ago completely breaks RX on the AD9361. Prior commits of this file works perfectly for us, but the changes in this commit breaks it. When I look at the rx_frame signals in a logic analyze at runtime, the case statements for delineation can not possibly work. This is an RTL bug, tool and software versions should not matter here.

Used Software: No-OS Tool version: Vivado 2019.1.3 HDL Release version hdl_2019_r2 Software Release version 2019_r2

[dmitrii-galantsev]

Affirmative, can observe in my setup as well. 👎

[johnathan-convertino-afrl]

Change lines 222 to 229 in hdl/library/axi_ad9361/xilinx /axi_ad9361_lvds_if.v to the snippet below.

always @(posedge l_clk) begin
    rx_error_r1 <= ~(({rx_frame, rx_frame_s} == 4'b1100) || ({rx_frame, rx_frame_s} == 4'b0011));
    rx_error_r2 <= ~(({rx_frame, rx_frame_s} == 4'b1111) || ({rx_frame, rx_frame_s} == 4'b1100) ||
                     ({rx_frame, rx_frame_s} == 4'b0000) || ({rx_frame, rx_frame_s} == 4'b0011));
  end

  always @(posedge l_clk) begin
      case ({rx_r1_mode, rx_frame, rx_frame_s})

A few years back I ran into this issue and fixed it for my own HDL project. The original code using rx_frame_s only makes zero sense, as its only a 2 bit vector being compared to a 4 bit vector. Fix is based on the previous code. I also changed the order of the case statement as well.

Wish I had documented the changes better, my commits don't reflect the reasons. It was bundled with other changes involved in arria10 timing. Lesson, make better commits.

My file can be found at: https://github.com/johnathan-convertino-afrl/hdl/blob/hdl_quartus_pro_2023_r1/library/axi_ad9361/axi_ad9361_lvds_if.v

[IuliaCMoldovan]

Hi all,

Thank you for letting us know, and apologies for the very late reply; somehow we missed this. We don't really track the GitHub issues, as most of the inquiries and comments come through our EngineerZone forum. This will be fixed in the future commits.

Best regards, Iulia