Unexpected voltage on output when changing modes after sampling

[jmball]

Running measurements in HI_Z mode seems to unexpectedly set the DAC to ~2V when re-enabling SVMI mode.

Here's a minimal program, which demonstrates the issue:

import pysmu

s = pysmu.Session()

# measure in SVMI mode
s.devices[0].channels["A"].write([0.5])
s.devices[0].channels["A"].mode = pysmu.Mode.SVMI
s.start(1)
print(f"SVMI data: {s.read(1, 1000)}")

# measure in HI_Z mode
s.devices[0].channels["A"].mode = pysmu.Mode.HI_Z
s.start(1)
print(f"HI_Z data: {s.read(1, 1000)}")

# re-enabling SVMI mode now puts 2V on the output before a subsequent measurement
s.devices[0].channels["A"].mode = pysmu.Mode.SVMI

I have tried changing the default DAC value in firmware as described in issue [#186] but this only affects the DAC immediately after power-on. It has no effect on what happens after the HI_Z measurement.

I've also tried clearing the DAC using control transfers to cycle the CLR pin as described in the datasheet:

# set DAC clear pin low
s.devices[0].ctrl_transfer(0x40, 0x50, 15, 0, 0, 1, 100)

# set DAC clear pin high, should clear output to 0V but doesn't
s.devices[0].ctrl_transfer(0x40, 0x51, 15, 0, 0, 1, 100)

which has no effect.

I've also tried adding a custom control transfer code to firmware that when written to writes the default settings to the DAC. This also has no effect.

Similarly to issue [#186], I think allowing a non-zero voltage that hasn't been requested to show up on the output risks damaging the device under test between measurement modes. Is there a way I can prevent this 2V showing up when SVMI mode is enabled after a measurement in HI_Z mode?