Wip/bl/ad3552r

[spectrum70]

Pull Request Description

Add zedboard Xilinx support to ad3552r driver and demo. Tested generic-spi, 1024 samples syn waves visible on both channels, with or without crc. Further improvements will follow.

PR Type

• [ ] Bug fix (change that fixes an issue)
• [x] New feature (change that adds new functionality)
• [ ] Breaking change (has dependencies in other repos or will cause CI to fail)

PR Checklist

• [ x] I have followed the Coding style guidelines
• [x] I have performed a self-review of the changes
• [x] I have commented my code, at least hard-to-understand parts
• [ ] I have build all projects affected by the changes in this PR
• [ ] I have tested in hardware affected projects, at the relevant boards Could not test on SDP-H1 right now, my setup is with Zedboard.
• [x] I have signed off all commits from this PR
• [ ] I have updated the documentation (wiki pages, ReadMe etc), if applies

[spectrum70]

Adding used system_top
system_top.xsa.gz

[CLAassistant]

All committers have signed the CLA.

[spectrum70]

Hi, in this phase i worked with https://github.com/adi-ses/sea-misc/blob/ad3552r_classic_spi/AD3552R-PRJ/hdl/system_top.xsa

So this fixes are for "generic-spi".

It has been discussed that a new hdl for both generic-spi and quad-spi will be implemented, not sure of the development state.

[spectrum70]

Pushed V2:

• removed all ifdefs,
• add asynchronous mode support,
• add a non functional variable naming fix.

[buha]

@spectrum70 I think it's good to merge but there was probably a mixup with Git identities and you need to sign the CLA (see the CLA Assistant bot comment above).

[AAndrisa]

/AzurePipelines run

[azure-pipelines[bot]]

Azure Pipelines successfully started running 2 pipeline(s).

[buha]

/AzurePipelines run

[azure-pipelines[bot]]

Azure Pipelines successfully started running 2 pipeline(s).