Closed podgori closed 6 months ago
Generated documentation for this PR is available at Link
1 424 tests ±0 255 :heavy_check_mark: ±0 9m 13s :stopwatch: ±0s 1 suites ±0 1 169 :zzz: ±0 1 files ±0 0 :x: ±0
Results for commit c097476c. ± Comparison against base commit 89d94fd8.
1 436 tests +12 255 :heavy_check_mark: ± 0 9m 14s :stopwatch: -1s 1 suites ± 0 1 181 :zzz: +12 1 files ± 0 0 :x: ± 0
Results for commit 46b54506. ± Comparison against base commit 89d94fd8.
:recycle: This comment has been updated with latest results.
@podgori how is this different than the existing TDD class?
This class is specific to the Generic TDD engine, the new scalable and standalone TDD IP, which aims to reduce the naming confusion around the existing TDD core built for AD9361, as well as expanding its number of output channels for systems which require more than six controlling signals (up to 32 channels). As such:
Can we replace the existing design (adi.tdd) with this one?
Can we replace the existing design (adi.tdd) with this one?
As discussed, we can leave these 2 classes separate for now.
Description
Adding support for TDDN:
Type of change
How has this been tested?
The example script was tested on Pluto in Phaser mode. The TDD configuration and functionality from pluto_tddn.py example was validated and tested with an oscilloscope.
Documentation
TDDN wiki page: https://wiki.analog.com/resources/fpga/docs/axi_tdd
Checklist: