synthesis issue

[vijayank88]

@andars I'm unable to synthesis your RTL and facing following issue during yosys synthesis.

12.1. Analyzing design hierarchy..
Top module:  \top_4ft4
Used module:     \wb_system
Used module:         \ram
Used module:         \rom
Used module:         \cpu
Used module:             \datapath
Used module:                 \alu
Used module:             \pc_stack
Used module:             \cpu_control
Parameter \CHIP_ID = 1'0

12.2. Executing AST frontend in derive mode using pre-parsed AST for module `\ram'.
Parameter \CHIP_ID = 1'0
Generating RTLIL representation for module `$paramod\ram\CHIP_ID=1'0'.
Parameter \CHIP_ID = 1'0
Found cached RTLIL representation for module `$paramod\ram\CHIP_ID=1'0'.
Parameter \CHIP_ID = 0
Parameter \ROM_FILE = 592'0010111101101111011100000110010101101110011011000110000101101110011001010010111101100100011001010111001101101001011001110110111001110011001011110110110101110000011101110011010101011111001101000110011001110100001101000010111101101111011100000110010101101110011011000110000101101110011001010010111100110100011001100111010000110100001011110010111000101110001011110010111000101110001011110111011001100101011100100110100101101100011011110110011100101111011100100111010001101100001011110011010001100110011101000011010001011111011100100110111101101101010111110011000000101110011010000110010101111000

12.3. Executing AST frontend in derive mode using pre-parsed AST for module `\rom'.
Parameter \CHIP_ID = 0
Parameter \ROM_FILE = 592'0010111101101111011100000110010101101110011011000110000101101110011001010010111101100100011001010111001101101001011001110110111001110011001011110110110101110000011101110011010101011111001101000110011001110100001101000010111101101111011100000110010101101110011011000110000101101110011001010010111100110100011001100111010000110100001011110010111000101110001011110010111000101110001011110111011001100101011100100110100101101100011011110110011100101111011100100111010001101100001011110011010001100110011101000011010001011111011100100110111101101101010111110011000000101110011010000110010101111000
Generating RTLIL representation for module `$paramod$18e29a839794e09622cf8a0c1aa234cbf1134af2\rom'.
/openlane/designs/mpw5_4ft4/openlane/4ft4/../../4ft4/rtl/rom.v:0: ERROR: Can not open file `/openlane/designs/mpw5_4ft4/openlane/4ft4/../../verilog/rtl/4ft4_rom_0.hex` for \$readmemh.

Is that working fine at your end?

[andars]

Hi, thanks for reporting this.

I missed adding this .hex file. (I see now that the base caravel project .gitignore has a pattern to ignore all .hex)

I'll push an update over in https://github.com/andars/caravel-4ft4.

[andars]

Added 4ft4_rom_0.hex in https://github.com/andars/caravel-4ft4/commit/e54588b6d107d401aa7d8847ffc44e672eceeb3b

fwiw, I should probably change rom.v so the .hex files are not needed during synthesis (since AFAIK the initial block gets dropped anyway), but I think that commit should fix this failure.