incorrect event-counter scheduling on Icelake

andikleen / pmu-tools

Intel PMU profiling tools

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incorrect event-counter scheduling on Icelake #414

Closed aayasin closed 2 years ago

aayasin commented 2 years ago

The events CYCLE_ACTIVITY.STALLS_L* are restricted to counters 0-3 starting Icelake PMU. Latest toplev with TMA 4.3 support scheduled these two events twice in two groups:

CYCLE_ACTIVITY.STALLS_L1D_MISS
CYCLE_ACTIVITY.STALLS_L2_MISS
CYCLE_ACTIVITY.STALLS_L3_MISS

One group schedules them on incorrect counters as highlighted in figure! toplev-sched-icl

andikleen commented 2 years ago

Do you mean because they're in the end of the group? perf doesn't require the input to be the same order as what is put into the final counters, the kernel fixes it up. So I think that's ok.