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andkorzh / OLD-Verilog-MOS6502

A clock-accurate FPGA clone of the NMOs processor 6502, created on the basis of reverse engineering.
GNU General Public License v3.0
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drop in replacement? #1

Open robertgida opened 1 month ago

robertgida commented 1 month ago

Hello, it seems very interesting. Can you tell me is it possible to make a mos6502 cpu drop in replacement with this core and with a cpld? I know, there are plenty of real 6502 cpus around, but you know... why not? :)

Br, Sandor

andkorzh commented 4 weeks ago

Hi! No problem to assemble this project in CPLD. After all the edits and debugging it has spread a bit across resources and takes up 578 CPLD cells. Which is 8 cells more than Alterа EPM570. However, if you optimize it a bit it should fit, or use a more capacious CPLD.

andkorzh commented 4 weeks ago

This design was tested in the NES 2A03 core on FPGA. I also tested it with the Klauss Dorman test and the test was passed successfully. I think there will be no problems with CPLD. :)

andkorzh commented 4 weeks ago

I optimized the code a bit and now it fits into the Altera EPM570 CPLD. However, I had to give up the SO pin. It is rarely needed in practice and I decided to sacrifice it. The project in Quartus is available in the release.

robertgida commented 4 weeks ago

Thanks. I will try to tinkering with it. :)

robertgida commented 4 weeks ago

Wow, you really used a shoe spoon to fit in. Total logic elements 570/570, 100% :)

andkorzh commented 4 weeks ago

Unfortunately, it couldn't be done without a shoehorn :)). Keep me updated on your adventures with the CPLD 6502.

robertgida commented 4 weeks ago

I'll do. As I remember, there is some test pcb around for an other project with 570, just needs some fixing, bodge wiring, etc, but definitely can try it.