MASTER TODO - Githubissues

TODO:

[x] Kill symbol table? - no: still needed to detect name collision between ports/wires/sub-modules
[x] Review inner/outer aliases, primary names etc. for ports
[x] what is Module.name_lookup? - don't know: deleted
[ ] XNet.names is needed at all?
[ ] Clear netlist reference from Module
[x] Deal with Port.rhs_name -> probably need something along the lines that's in Module._generate() now, except moved to the port.
[x] inner_aliases: needed until xnet name population happens. attribute is deleted afterwards
[x] inner_auto_name
[ ] has_explicit_name on Port/Wire
[x] outer_aliases: needed until xnet name population happens. attribute is deleted afterwards
[x] outer_auto_name
[x] interface_name: new name on Ports (though it leaks into wires unfortunately) to denote the name on the Module interface
[x] Module.has_user_assigned_name -> renamed to has_explicit_name
[x] get_inline_block should use get_lhs_name for statements and add_rhs_expression for expressions. -> done differently, but done

[ ] better error messages
[x] fix getitem in a LHS context
[x] Empty the Module namespace as much as possible
[x] Finish @module decorators
[x] @module should use signature names for inputs
[x] clean up Tracer and its name creation (maybe default to no_trace?)
[x] We should not attempt to propagate types early. There's a place for that in elaborate, so we shouldn't try to be smart about it in ex. getitem

[x] Enum port types - this needs the re-introduction of types that generate RTL as interfaces and structs used to be able to.
[x] Need type-conversion, most importantly from Number to Enum
[x] PortType --> NetType
[x] PortBase --> Junction
[x] Wire --> not based on Port, but Junction
[ ] Need type-cast in a general way
[x] RAMs and ROMs
[ ] Alternative generation of Select* statements (inline statements instead of expressions)
[x] FSM: use const_convert_lookup (or similar) to find undelying type of state constants
[x] FSM: use underlying state type to come up with final state type. Use get_common_net_type and PortType.result_type(operation="SELECT") to achieve this.
[x] FSM: Junction has a has_driver member. Maybe a similar (get_driver) thingy could be created and used to generate the drawing.
[ ] FIFOs
[ ] CDCs
[x] The above probably needs interfaces, so interfaces
[ ] Replace yield with async?
[ ] Register generator, as in configuration registers attached to a bus.
[ ] Somehow fix mixed accesses. Such as out_a = in_a.a.b[9:4][0].c.d and of course the reverse as well.

[ ] Re-use Silicon as the SKiDL (https://xess.com/skidl/docs/_site/) variant of the idea, one that's used for SCH replacement

[ ] Somehow publish Jupyter notebooks
[ ] Add DarwIO (https://github.com/QuantStack/jupyterlab-drawio) to Jupyter
[ ] Add WaveDrom (https://wavedrom.com/editor.html) output support to Silicon and Jupyter

Tests to add:

[ ] Type-specifying input ports later on for all gates (that is binding through .-notation instead of all)
[ ] Same as above, but with sub_ports: and.input_3[3] = ...
[ ] Binding ports to abstract number types or ports with abstract number types
[ ] Try to finalize port types after things are frozen. Maybe we should allow that? Maybe we should even encourage that, but automatically finalizing port types before freezing the port list???

andrastantos / silicon