Instruction latencies are wrong with fused rip-relative loads

[TellowKrinkle]

(Note: Tested whatever version is on https://uica.uops.info, none locally) Instructions that use rip-relative addressing seem to be treated as if they had 1 cycle of latency.

e.g.

vpmulhw ymm12, ymm12, ymmword ptr [rip+0x14b]
vpmulhw ymm12, ymm12, ymmword ptr [rax+0x14b]

On uica.uops.info: https://bit.ly/3H3YsAR

Expected:

• The rip and rax versions have the same distance between the D and E markers (5 cycles according to uops.info)
• The predicted throughput is 10 cycles, since one iteration is two dependent 5-cycle instructions

Actual:

• The predicted throughput is 6 cycles