Operand size mismatch with `vgatherdps` using Intel syntax

[chriselrod]

.LBB0_5:                                # %L50
                                        # =>This Inner Loop Header: Depth=1
        vmovups zmm1, zmmword ptr [r11 + 4*rdi]
        vmovups zmm2, zmmword ptr [r11 + 4*rdi + 64]
        vmovups zmm3, zmmword ptr [r11 + 4*rdi + 128]
        vmovups zmm4, zmmword ptr [r11 + 4*rdi + 192]
        kxnorw  k1, k0, k0
        vxorps  xmm5, xmm5, xmm5
        vgatherdps      zmm5 {k1}, zmmword ptr [rax + 4*zmm1]
        kxnorw  k1, k0, k0
        vxorps  xmm1, xmm1, xmm1
        vgatherdps      zmm1 {k1}, zmmword ptr [rax + 4*zmm2]
        vfmsub132ps     zmm5, zmm0, zmmword ptr [rdx + 4*rdi] # zmm5 = (zmm5 * mem) - zmm0
        vfmadd132ps     zmm1, zmm5, zmmword ptr [rdx + 4*rdi + 64] # zmm1 = (zmm1 * mem) + zmm5
        kxnorw  k1, k0, k0
        vxorps  xmm2, xmm2, xmm2
        vgatherdps      zmm2 {k1}, zmmword ptr [rax + 4*zmm3]
        kxnorw  k1, k0, k0
        vxorps  xmm0, xmm0, xmm0
        vgatherdps      zmm0 {k1}, zmmword ptr [rax + 4*zmm4]
        vfmadd132ps     zmm2, zmm1, zmmword ptr [rdx + 4*rdi + 128] # zmm2 = (zmm2 * mem) + zmm1
        vfnmsub132ps    zmm0, zmm2, zmmword ptr [rdx + 4*rdi + 192] # zmm0 = -(zmm0 * mem) - zmm2
        add     rdi, 64
        add     rsi, -4
        jne     .LBB0_5

Results in

/tmp/ee3af94421ca41f38d2808205839a8bc.asm: Assembler messages:
/tmp/ee3af94421ca41f38d2808205839a8bc.asm:10: Error: operand size mismatch for `vgatherdps'
/tmp/ee3af94421ca41f38d2808205839a8bc.asm:13: Error: operand size mismatch for `vgatherdps'
/tmp/ee3af94421ca41f38d2808205839a8bc.asm:18: Error: operand size mismatch for `vgatherdps'
/tmp/ee3af94421ca41f38d2808205839a8bc.asm:21: Error: operand size mismatch for `vgatherdps'

Switching to ATT yields

.LBB0_5:                                # %L50
                                        # =>This Inner Loop Header: Depth=1
        vmovups (%r11,%rdi,4), %zmm1
        vmovups 64(%r11,%rdi,4), %zmm2
        vmovups 128(%r11,%rdi,4), %zmm3
        vmovups 192(%r11,%rdi,4), %zmm4
        kxnorw  %k0, %k0, %k1
        vxorps  %xmm5, %xmm5, %xmm5
        vgatherdps      (%rax,%zmm1,4), %zmm5 {%k1}
        kxnorw  %k0, %k0, %k1
        vxorps  %xmm1, %xmm1, %xmm1
        vgatherdps      (%rax,%zmm2,4), %zmm1 {%k1}
        vfmsub132ps     (%rdx,%rdi,4), %zmm0, %zmm5 # zmm5 = (zmm5 * mem) - zmm0
        vfmadd132ps     64(%rdx,%rdi,4), %zmm5, %zmm1 # zmm1 = (zmm1 * mem) + zmm5
        kxnorw  %k0, %k0, %k1
        vxorps  %xmm2, %xmm2, %xmm2
        vgatherdps      (%rax,%zmm3,4), %zmm2 {%k1}
        kxnorw  %k0, %k0, %k1
        vxorps  %xmm0, %xmm0, %xmm0
        vgatherdps      (%rax,%zmm4,4), %zmm0 {%k1}
        vfmadd132ps     128(%rdx,%rdi,4), %zmm1, %zmm2 # zmm2 = (zmm2 * mem) + zmm1
        vfnmsub132ps    192(%rdx,%rdi,4), %zmm2, %zmm0 # zmm0 = -(zmm0 * mem) - zmm2
        addq    $64, %rdi
        addq    $-4, %rsi
        jne     .LBB0_5

Adding .intel_syntax to the Intel version and running llvm-mca locally also works (but I prefer uica over llvm-mca).

[amonakov]

GNU as doesn't accept zmmword ptr in the context of vgather (and I agree: it doesn't seem to make sense there). Just removing zmmword ptr is sufficient to make the code assemble.

(you might want to ask LLVM to avoid emitting the unnecessary zmmword ptr)

[andreas-abel]

Closing this, as this is something that would need to be changed in GNU as and not in uiCA.