andrewrothman / mina

An education-focused CPU definition, assembler, virtual machine, and debugger
MIT License
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CPU architecture #1

Open andrewrothman opened 9 years ago

andrewrothman commented 9 years ago

Base design off of simple ARM architecture.

Leave out most sugar instructions. Try to keep the opcodes down to a minimum.

32-bit is the goal. 16-bit if possible. 8-bit if absolutely necessary.

andrewrothman commented 9 years ago

Mathematical operators are a must. Setting and getting to/from registers and memory is also important.

andrewrothman commented 9 years ago

I'd like to have a couple of instructions for use in making actual programs... maybe:

PUT <base (optional; can be 2, 10, or 16, default is 10)> - prints the value at the specified memory address as decimal

GET <base (optional; can be 2, 10, or 16, default 10 unless otherwise prefixed... if specified disable prefixing) - gets a value and stores it into the specified register

DISPLAY - prints all characters until a 00 is encountered to the console BEEP - plays a beep sound or displays the text "beep" in the console

andrewrothman commented 9 years ago

Maybe some graphics display out of memory-mapped io? This would be interesting. Also we could have the keyboard and mouse under mmio.

andrewrothman commented 9 years ago

Yes to memory mapped io. Map a graphics display, a cursor, and a keyboard.

andrewrothman commented 9 years ago

Also have space for additional Mina official memory mapped io, and after the blank space for compatibility, allow additional memory mapped io features that each individual implementation may provide and that may be unofficial (some vms might want a higher resolution, or a joystick, or something else.

andrewrothman commented 9 years ago

Start memory at an offset after the blank space. Set a standard memory size available on all official implementations, and allow the user to configure the space provided.

andrewrothman commented 9 years ago

Also deal with register addressing. If we're thinking of a 32 bit machine, then we need an equivalent of EAX, AX, AH, and AL for each register.

If 16 bit, only AX, AH, and AL are needed.

Maybe use an addressing scheme such as 1 (EAX), 1:1 (AX), 1:1:1 (AL), 1:1:2 (AH).

Clearly separate which registers can be used by applications, which can be used by kernels, and which can be used by compilers or runtimes.

andrewrothman commented 9 years ago

Yes to memory mapped graphics. Also have memory mapped audio (very simple chiptune-like) and persistent storage (some small data file that gets saved on disk and reloaded when a program is run again).

andrewrothman commented 9 years ago

Also remove the BEEP command. It can become confusing with mm-audio.

andrewrothman commented 9 years ago

mm-random number generator.

andrewrothman commented 9 years ago

Maybe have sprites? Whatever is needed to display good graphics and games and stuff.

andrewrothman commented 9 years ago

Also maybe use a.higher.lower and a.higher for register addressing.

andrewrothman commented 9 years ago

Two's complement will be used to represent signed numbers.

If possible try to use a single opcode per instruction for both signed and unsigned numbers. Again, this might not be possible.

andrewrothman commented 9 years ago

CMP instruction to compare two constant, register, or memory values. Sets the flags register with appropriate result.

JMP and conditional JMP instructions that point to memory location of next instruction. Sets current_instruction register with new instruction address. Conditionals read in flags register.

andrewrothman commented 9 years ago

INC and DEC instructions.

AND, OR, XOR, NOT.

Don't include NOR. It's not necessary.

andrewrothman commented 9 years ago

Look into hardware/software interrupts.

andrewrothman commented 9 years ago

Maybe send interrupts instead of using memory-mapped io for certain functionality? I'm not sure about this.

andrewrothman commented 9 years ago

Target 16 bit. Also allow addressing of 8 bits.

andrewrothman commented 9 years ago

I want 20 general purpose registers, along with flags, current_instruction, and other special registers.

andrewrothman commented 9 years ago

https://fail0verflow.com/blog/2012/dcpu-16-review.html

andrewrothman commented 9 years ago

http://0x10cforum.com/forum/m/4932880/viewthread/2895442-17-updated-dcpu16-specs-hardware

andrewrothman commented 9 years ago

Right and left shift support.

andrewrothman commented 9 years ago

NOP instruction

andrewrothman commented 9 years ago

http://wiki.nesdev.com/w/index.php/CPU

andrewrothman commented 9 years ago

No interrupts for now. All I/O can be accomplished by memory-mapped addresses, and there is no real asynchronous I/O that is critical enough that this concept needs to be added.

andrewrothman commented 9 years ago

http://marc.rawer.de/Gameboy/Docs/GBCPUman.pdf

andrewrothman commented 9 years ago

https://en.wikipedia.org/wiki/History_of_video_game_consoles_(fourth_generation)

andrewrothman commented 9 years ago

Machine code should allow program name, version, author name, and website url. See GB 2.5.4 ^^.

andrewrothman commented 9 years ago

See GB command index.

andrewrothman commented 9 years ago

Bisqwit's NES emulator in C++ tutorial video series:

https://www.youtube.com/watch?v=y71lli8MS8s https://www.youtube.com/watch?v=XZWw745wPXY